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1 rev. 4157c?aero?06/03 features organized as 2m x 8 bits single 3.3v power supply stacks of 16 sram 128k x 865609e die access time: 40 ns very low power consumption ? active: 100 mw (typ) ? standby: 1 mw (typ) ttl-compatible inputs and outputs die designed on 0.35 micron process latch-up immune 100 krads (tm1019.5) wide temperature range 55 c to +125 c built and tested by 3d+, using 3d+ die stacking technology description the AT61162E is a rad tolerant module, highly-integrated and very low-power cmos static ram organized as 2m x 8 bits. it is organized with 16 banks of 1 mbit. each bank has a 8-bit interface and is selected with 16 specific cs : 0 - 15. banks are selectable by pairs with 8 specific bs: 0 - 7. this module takes full benefit of the 3d+ cube technology, and it is assembled and tested by 3d+, using atmel 65609e 1-mbit sram die: it is built with 8 layers, each one housing 2 dies. 10 nf decoupling capacitors are embedded for each memory die. this module brings the solution to applications where fast computing is as mandatory as low power consumption, for example: space electronics, portable instruments, or embarked systems. AT61162E is processed according to the methods of the latest revision of the mil prf 38535, qml n (qml q counterpart for plastic). the package is a 64 gull wing pins dual in line, 11 mm wide, 28 mm long and 14.3 mm height and 0.8 mm pin pitch. rad hard 2-mbit x 8 sram cube AT61162E preliminary
2 AT61162E 4157c ? aero ? 06/03 block diagram pin configuration a (0:16) we oe cs2 cs2 bs0 cs 0.1 cs 0.0 bank 0 i/o (0:7) cs 1 chip 1 chip 0 cs 1 cs 1.0 cs 1.1 bs1 cs 7.0 cs 7.1 bs7 cs2 cs 1 cs2 cs 1 cs2 cs 1 cs2 cs 1 bank 1 bank 7 a (0:16) we oe i/o (0:7) a (0:16) we oe i/o (0:7) a (0:16) we oe i/o (0:7) a (0:16) we oe i/o (0:7) a (0:16) we oe i/o (0:7) a (0:16) we oe i/o (0:7) chip 1 chip 1 chip 0 chip 0 cs 7.0 cs 6.0 cs 5.0 cs 4.0 cs 3.0 cs 2.0 cs 1.0 cs 0.0 cs 0.1 cs 1.1 cs 2.1 cs 3.1 cs 4.1 cs 5.1 cs 6.1 cs 7.1 bs 7 bs 6 bs 5 bs 4 bs 3 bs 2 bs 1 bs 0
3 AT61162E 4157c ? aero ? 06/03 pin description truth table pin name function ao - a16 address inputs we write enable oe output enable cs 0.0 - cs 7.1 chip select 1 bs0 - bs7 chip select 2 i/o0 - i/o7 data inputs/outputs v cc 3.3v power gnd ground nc no connection cs x.x bs x we oe inputs/ outputs mode all cs h ??? z deselect/ power-down ? all bs l ?? z deselect/ power-down cs y.z: l other cs : h bsy: h other bs: ? h l data out read (bank y.z selected) cs y.z: l cs y.z: h other cs : ? bsy: h other bs: l cs y.z: l other cs : h bsy: h other bs: ? l ? data in write (bank y.z selected) cs y.z: l cs y.z: h other cs : ? bsy: h other bs: l cs y.z: l other cs : h bsy: h other bs: ? h h z output disable cs y.z: l cs y.z: h other cs : ? bsy: h other bs: l
4 AT61162E 4157c ? aero ? 06/03 electrical characteristics absolute maximum ratings* operating range recommended dc operating conditions capacitance supply voltage to gnd potential............................ 0.5 to +5v dc input voltage gnd ........................... gnd -0.3 to v cc 0.3v dc output voltage high-z-state gnd ... gnd -0.3 to v cc +0.3v storage temperature ......................................... -65 to +150 c output current into outputs (low)................................. 20 ma electro statics discharge voltage (mil std 883d method 3015.3).................................. >1500v *note: stresses beyond those listed under "absolute maxi- mum ratings ? may cause permanent damage to the device. this is a stress rating only and functional oper- ation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. operating temperature operating voltage military -55 c to 125 c3.3v 0.3v parameter description min typ max units v cc supply voltage 3 3.3 3.6 v gnd ground 0 0 0 v v ih input high voltage 2.2 - v cc +0.3 v v il input low voltage gnd-0.3 0.0 0.8 v parameter description min typ max unit c in (1) input low voltage - - 8 pf c out (1) output high voltage - - 8 pf note: 1. guaranteed but not tested.
5 AT61162E 4157c ? aero ? 06/03 dc parameters consumption parameter description min typ max unit i ix (1) 1. gnd < v in < v cc , gnd < v out < v cc output disabled. input leakage current -16 - 16 a i oz (1) output leakage current -16 - 16 a v ol (2) 2. v cc min. iol = 1 ma. output low voltage - - 0.4 v v oh (3) 3. v cc min. ioh = -0.5 ma. output high voltage 2.4 - - v symbol description 61162e-35 unit value iccsb (1) 1. cs 0.0 - cs 7.1 > v ih or bs 0 - bs7 < v il and cs 0.0 - cs 7.1 < v il . standby supply current 40 ma max iccsb 1 (2) 2. cs 0.0 > v cc - 0.3v or, bs 0 - bs7 < gnd + 0.3v and cs 0.0 - cs 7.1 < 0.2v standby supply current 32 ma max iccop (3) 3. one bank active (f = 1/t avav , i out = 0 ma, w = oe = v ih , v in = gnd/v cc , v cc max.), other banks stand by ttl (note 1) or cmos (note 2). dynamic operating current 90 ma max
6 AT61162E 4157c ? aero ? 06/03 write cycle note: 1. parameters guaranteed, not tested, with output loading 5 pf (see 1b in figure: ac test loads waveforms). read cycle note: 1. parameters guaranteed, not tested, with output loading 5 pf (see 1b in page figure: ac test loads waveforms). symbol parameter 61162e-40 unit value t avaw write cycle time 40 ns min t avwl address set-up time 0 ns min t avwh address valid to end of write 35 ns min t dvwh data set-up time 35 ns min t e1lwh cs 1 low to write end 35 ns min t e2hwh cs 2 high to write end 35 ns min t wlqz write low to high-z (1) 20 ns max t wlwh write pulse width 35 ns min t whax address hold from to end of write +3 ns min t whdx data hold time 0 ns min t whqx write high to low-z (1) 0nsmin symbol parameter 61162e-40 unit value t avav read cycle time 40 ns min t avqv address access time 40 ns max t avqx address valid to low-z 3 ns min t e1lqv chip-select 1 access time 40 ns max t e1lqx cs 1 low to low-z (1) 3nsmin t e1hqz cs 1 high to high-z (1) 20 ns max t e2hqv chip-select 2 access time 40 ns max t e2hqx cs 2 high to low-z (1) 3nsmin t e2lqz cs 2 low to high-z (1) 20 ns max t glqv output enable access time 15 ns max t glqx oe low to low-z (1) 0nsmin t ghqz oe high to high-z (1) 10 ns max
7 AT61162E 4157c ? aero ? 06/03 ac parameters ac test conditions ac test loads waveforms input pulse levels: ....................................................... gnd to 3.0v input rise/fall times: .................................................. 5 ns input timing reference levels: ................................... 1.5v output loading i ol /i oh (see figures 1a and 1b)............ +30 pf figure 1a figure 1b figure 2 r1 2552 r1 2552 2824 2824 1340 3.3v 3.3v
8 AT61162E 4157c ? aero ? 06/03 data retention mode atmel cmos ram ? s are designed with battery backup in mind. data retention voltage and supply current are guaranteed over temperature. the following rules ensure data retention: 1. during data retention cs must be held high within v cc to v cc -0.2v or, chip select bs must be held down within gnd to gnd +0.2v. 2. output enable (oe ) should be held high to keep the ram outputs high imped- ance, minimizing power dissipation. 3. during power up and power down transitions cs and oe must be kept between v cc + 0.3v and 70% of v cc , or with bs between gnd and gnd -0.3v. 4. the ram can begin operation > tr ns after v cc reaches the minimum operation voltages (3v). timing data retention characteristics notes: 1. t avav = read cycle time 2. all cs = v cc or all bs = cs = gnd, v in = gnd/v cc . 3v 3v bs parameter description min typical t a = 25 cmax unit v ccdr v cc for data retention 2.0 ?? v t cdr chip deselect to data retention time 0.0 ?? ns t r operation recovery time t avav (1) ?? ns i ccdr1 (2) data retention current at 2.0v ? 0.160 16 ma
9 AT61162E 4157c ? aero ? 06/03 figure 1. write cycle 1. w controlled, oe high during write figure 2. write cycle 2. w controlled, oe low
10 AT61162E 4157c ? aero ? 06/03 figure 3. write cycle 3. cs 1 or cs2 controlled note: the internal write time of the memory is defined by the overlap of cs 1 low and cs 2 high and we low. both signals must be activated to initiate a write and either signal can terminate a write by going in actived. the data input setup and hold timing should be referenced to the activated edge of the signal that terminates the write. data out is high impedance if oe = v ih . figure 4. read cycle nb 1 figure 5. read cycle nb 2
11 AT61162E 4157c ? aero ? 06/03 figure 6. read cycle nb 3 d
12 AT61162E 4157c ? aero ? 06/03 test tools ordering information supplier reference number enplas ots - 64 - 0.8 - 04 reference number temperature range speed package quality flow AT61162E-pm40mmn -55 to +125 c 40 ns cube 64 pins qml n AT61162E-pm40m-e 25 c 40 ns cube 64 pins engineering samples
13 AT61162E 4157c ? aero ? 06/03 package drawing dimensions (mm) min max a 14.0 14.60 d 13.60 13.80 d1 10.75 11.15 e 27.80 28.20 f7.5 e 0.80 0.35 e1
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